ADVANCED VEHICLE TECHNOLOGIES, Inc.
AVT-931 Dual J1850 Interface
(VPW and PWM)
PC/104 Unit Technical Summary

INTRODUCTION

The AVT-931 Dual J1850 Interface is a printed circuit board that implements both VPW and PWM versions of SAE specification J1850. It is a PC/104 form factor board designed for installation in a PC/104 computer "stack." The AVT-931 permits the user to directly connect the PC/104 computer to a vehicle for the purposes of testing, monitoring, data acquisition, and other operations.

The Society of Automotive Engineers (SAE) has adopted a specification known as J1850 “Class B Data Communications Network Interface.” This specification describes two forms of a multiplex bus structure intended for use in a vehicle. The two forms of this multiplex bus are known as Pulse Width Modulation (PWM) and Variable Pulse Width (VPW). The AVT-931 Dual Interface implements both versions of the J1850 standard (simultaneous operations are not permitted).

The AVT-931 Dual Interface provides the following functions:

The AVT-931 conforms to the Ford Motor Company Standard Corporate Protocol (SCP) which defines network traffic management, message construction, and other protocol issues. (The SCP specifies operations in PWM mode.) The AVT-931 is fully compatible with any similarly equipped Ford Motor Company or Mazda product.

When in VPW mode of operation the AVT-931 permits both transmit and receive operations at 4 times the normal speed (4X mode). Additionally, the AVT-931 supports block transfer mode. These modes of operation are not supported by the J1850 specification but may be required to be compatible with General Motors’ Class 2 system.

Installation and Connections

The AVT-931 is equipped with 16-bit stackthrough connectors and is easily installed in the host computer "stack." The board only connects to and uses the 8-bit ISA bus. The base or segment address of the board is switch selectable to anywhere in the first megabyte of memory space in the host. The base or segment address must be set prior to installation. There are no other installation requirements.

Connecting the AVT-931 to the subject vehicle is easily accomplished via a ribbon cable and our OBD-II compatible cable (available separately). Our OBD-II compatible cable is designed to mate directly with the subject vehicle. No other connections are required. The cable may be connected or disconnected at will without affecting the host computer.

No other connections or installation is required.

Hardware Configuration

The AVT-931 Dual Interface board is mapped into the memory space of the host computer. (It is not mapped into host I/O space.) The Interface board occupies only 16 bytes of memory space (of which only 3 bytes are used). The base or segment address of the AVT-931 Dual Interface board is selected by setting 16 on-board DIP switches. Any address in the first one megabyte of host memory space can be selected. It not recommended that an address within the first 640 KBytes be selected (this space is ‘holy’ to DOS). It is recommended that the board be set in the memory space reserved for a system monochrome display as this space is usually empty in most modern machines.

Specifications and Requirements

AVT-931 Hardware

The AVT-931 Dual J1850 Interface board is a four layer printed circuit board designed to be installed in a PC/104 compatible host computer. The board is equipped with 16-bit stackthrough connectors but only utilizes the 8-bit ISA bus. Through this connection the AVT-931 receives +5 and +12 VDC power from the host. Communications between the board and the host are also accomplished through this connection. The AVT-931 Dual Interface board also has a 16 pin header connector. Through this connector the AVT-931 is connected (via an appropriate ribbon cable and an OBD-II cable) to a subject vehicle’s OBD-II connector.

The heart of the unit is the Motorola MC68HC711KA2 microcontroller. This device utilizes an HC11 core with a bus speed of 4 MHz. The operational firmware is contained in on-board EPROM.

Other AVT-931 functional blocks include two FIFO’s, a PWM interface, a VPW interface, a bus multiplexer, electrical isolation of the host computer from the vehicle, and two hardware control/status registers. VPW mode operations utilize the Motorola MC68HC57 Data Link Controller (DLC) which includes the VPW bus transceiver function. PWM mode operations utilize the Motorola HBCC device and a Ford Motor Company PWM bus transceiver design.

The two FIFO’s on the AVT-931 are configured as a set of bi-directional mail boxes for message passing between the microcontroller and the host computer. Each FIFO is 2 KBytes deep and fully asynchronous. They facilitate communications between the host and the microcontroller while minimizing the risk of lost data and eliminating the requirement for real-time response from the host.

The electrical isolation barrier is depicted on the block diagram. The AVT-931 Dual Interface derives its operating power (+5 VDC and +12 VDC) from the host computer. Additionally, a connection exists between the AVT-931 and the subject vehicle unswitched battery positive (VBATT). This supply is diode isolated and electrically isolated from the host +12 VDC supply. This arrangement permits
normal AVT-931 operations even when not connected to a subject vehicle. When the AVT-931 is connected to a vehicle the VBATT connection provides a common positive supply for all network nodes.

Selecting the mode of operation for the AVT-931 is accomplished through software commands on the host computer. These commands result in writing appropriate values (via the ISA bus) into hardware control register #2 on the AVT-931 board. Bits in this register control the reset line and permit reading the full or empty status of the FIFOs.

AVT-931 Operation

The AVT-931 Dual Interface performs all data and protocol conversion functions permitting communications between the host and the subject vehicle. Communications between the AVT-931 and the subject vehicle are in conformance with SAE Standard J1850 and related standards and recommended practices. When in the PWM mode of operation, the AVT-931 is compliant with the Ford SCP. When in the VPW mode the unit is also capable of both transmit and receive operations at 4 times the normal speed (VPW 4x mode) as well as block transfers of data.

The AVT-931 is mapped into the memory space (not I/O space) of the host computer. The base address of the AVT-931 board is determined by the setting of two 8-bit DIP switches. All communications between the host and the AVT-931 are via the 8-bit ISA bus.

The structure and protocol of communications between the AVT-931 and the host computer are such that all data is transferred in packets. The size of each data packet varies from 1 byte to 16 bytes (inclusive). The first byte in each data packet is the header byte and is used to convey information only between the AVT-931 Dual Interface board and the host computer.

The header byte is divided into the upper nibble and lower nibble. The upper nibble indicates what information the data packet is conveying. The lower nibble is the count of the number of bytes that follow the header byte. The meaning of the upper nibble of the header byte depends on which direction the data packet is moving; whether to or from the host computer.

Messages from the host computer to the AVT-931 are known as Commands. Messages from the AVT-931 to the host computer are known as Responses. Please consult the latest revision of the User's Manual. Additionally, consult the latest revision of the Master Commands and Responses document for information on commands and operations supported by the AVT-931. Block transfers of data are supported via a special command, please consult the application note for block transfer operations. All of these documents are available from our web site, download page (Home | Products | Download).

ISA Bus Memory Map


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